Analog to digital converters (ADCs) convert an analog voltage input to a digital output, usually in binary code, at a certain sampling rate. ADCs have been implemented using various architectures including successive approximation, Sigma Delta, and bit-per-stage architectures. ADCs are commonly characterized by their resolution (the number of output levels, expressed in bits, to which they can quantize a signal), and their sampling rate.
In certain applications, it is necessary to increase the resolution of conventional analog-to-digital converters (ADCs) while maintaining a small size. In particular, maintaining a small size can be important in embedded applications, such as for ADCs embedded in accelerometers or micropower impact sensors. It is also desirable for an ADC to provide low power consumption and a variable resolution (e.g., a variable number of output bits).
It is difficult to increase the resolution of existing successive approximation analog-to-digital converters because such converters are already relatively large and would need to be enlarged further to accommodate 14 or more bits. Furthermore, additional trimming features may be required beyond 13 bits. Sigma-delta ADCs provide higher resolution, but at the expense of higher power consumption. Additionally, sigma-delta converters cannot usually be multiplexed. Binary bit-per-stage ADCs produce residue output signals with discontinuities corresponding to the points where the comparator changes state and causes a DAC to switch. These discontinuities in the residue output waveforms are a fundamental problem with such an architecture. Adequate settling time must be allowed for these transients to propagate through a stage and settle at the final comparator input, and as a result, it is difficult to make these architectures operate at high speeds.
Folding bit-per-stage ADCs avoid the discontinuity problems of the binary bit-per-stage architectures. F. D. Waldhauer presents an implementation of the folding architecture in U.S. Pat. No. 3,187,325. Waldhauer's implementation of the folding transfer function uses solid state operational amplifiers with diodes in the feedback loop. However, the Waldhauer implementation is best suited to low resolution applications because it has various independent error sources. For example, a cascade of Waldhauer's stages suffers from independent errors in every stage. Additionally, the Waldhauer implementation exhibits high power consumption. Therefore, there remains a need for ADCs that provide high resolution (e.g., 12 bits or more) while having low power consumption and a small size. Furthermore, there is a need for small low-power ADCs that have variable resolution.